People

Faculty

• Dr. Saroj Rout, Adjunct Professor and Mentor • Ph.D., Tufts University • B.E. & M.E., BITS-Pilani • 22 years of industry experience with more than 14 SoC projects • 10 years of research experience • 6 years of teaching • 8 patents • Author of "Active Metamaterials" a Springer-Nature publication • Research interest: Mixed-signal CMOS IC design: Data converters, Power management, low-power and low-noise audio-band front-ends. LinkedIn

• Dr. Santunu Sarangi, Assistant Professor • Ph.D., IIT Kharagpur • M.Tech, NIT Rourkela • 4 yers of indudtry experience • 4 years of teaching experience • 8 years of research experience • 7 publication • 2 patents(filed) • Research interest: Mixed-signal VLSI design: High-Speed SerDES, low-power bandgap, power management and data converters. LinkedIn

• Dr. Prakash Rout, Professor • Ph.D., NIT Rourkela • M.Tech., KIIT University • 16+ years of teaching experience • 12 years of research experience • 20 publication • Research interest: Mixed Signal VLSI Design, simulation of semiconductor devices.

• Dr. Biswajit Baral, Associate Professor • Ph.D., MAKAUT • M.Tech., BPUT Odisha • 16+ years of teaching experience • 12 years of research experience • 30 publication • Research interest: VLSI Design, semiconductor devices modeling and simulation study.

• Dr. Debasish Nayak, Sr. Assistant Professor • Ph.D, NIT Rourkela • M.Tech, BPUT Odisha • 10+ years of teaching experience • 8 years of research experience • 14 publication • Research interest: Mixed-signal VLSI design. Design, simulation and study of semiconductor dev.

• Dr. Sanghamitra Dash, Assistant Professor • Ph.D, Siksha ‘O' Anusandhan (Deemed to be University) • M.Tech, BPUT Odisha • 4+ years of teaching experience • 8 years of research experience • 54 publication • Research interest: Semiconductor Device Modeling, Bandgap Engineered Device and Reliability analysis of advanced heterostructure Devices.

• Mr. Sushant Kumar Pattanaik, Assistant Professor • Ph.D. (cont.), KIIT University, M.Tech, VSSUT Burla • 12+ years of teaching experience • 5+ years of research experience • 3+ years of industry experience • 10 publication • Research interest: Leakage minimization in adder circuits, SRAM design, area optimization of UART, embeded and IoT.

• Mr. Dhananjaya Tripathy, Assistant Professor • Ph.D. (cont.), NIT Rourkela, M.Tech, NIT Rourkela • 10+ years of teaching experience • 5+ years of research experience • 4 publication • Research interest: Analog VLSI design. Design, simulation and study of semiconductor devices.

• Mrs. Aradhana Raju, Assistant Professor • Ph.D. (cont.), KIIT University, M.Tech, BPUT Odisha • 15+ years of teaching experience • 5+ years of research experience • 4 publication • 1 patent Research interest: VLSI design and semiconductor devices.

• Mr. Prasant Swain, Technical Asst. Ph.D. (cont.), BPUT Odisha • M.Tech & B.Tech, BPUT Odisha • 13 years of academic experience • 4 years of industry experience • Area of Interest: VLSI Design Tool Technology, Embedded Systems Design and Linux system administration.

• Mr. Prabhat Kumar Singh, Technical Asst. Ph.D. (cont.), BPUT Odisha • M.Tech & B.Tech, BPUT Odisha • 13 years of academic experience • Area of Interest: VLSI Design Tool Technology, Embedded Systems Design and Linux system administration.

Trainees

Present Trainees

• Abhishek, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Akhilesh, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Aman Ranjan Pani, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Anuska maji, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Answesh Moharana, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Debasmita Sahoo, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Himanshu Bhusan Panda, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Jagan Kumar Patro, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Jyoti Prakash Pani, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Kirtirekha Behera, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Kishan Swain, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Mahesh, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Mayamugdha Mohanty, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Mohit Kumar Sahoo, BTech (EEE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Kumar Mrityunjay, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Om Pratihary, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Prayas Kumar, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Pratyush Behera, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Priyam Mishra, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Priyansh Kumar Sahoo, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Priyanshu Sahoo, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Priyanshu Panigrahi, BTech (EEE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Priyanshu Mishara, BTech (EEE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Rajeswar Prasad Panda, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Rituparna Rout, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Rudransh Kishore Sahoo, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Shruti Mahato, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Smrity Lata, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Subhalaxmi Pradhan, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Suhrid Dutta, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Sunanda Sahu, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Swayam Swroop Ojha, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2024 Batch • Doing traing with Advanced VLSI Lab in Digital and Analog VLSI Circuit Design domain • Project: Design and implementation of a simple 8-bit MIPS Microprocessor. • LinkedIn

• Debarchan Swain, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of I/O circuits in 180nm CMOS technology. • LinkedIn

• Rudra Narayan Sahu, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of I/O circuits in 180nm CMOS technology. • LinkedIn

• Tusar Nayak, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of I/O circuits in 180nm CMOS technology. • LinkedIn

• Rutucharya Panda, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of I/O circuits in 180nm CMOS technology. • LinkedIn

• Erica Banerjee, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Currently doing internship at Micron Technology in SCRIBE Layout domain • LinkedIn

• Punyatoya Mohanty, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Currently doing internship at STMicroelectronics in PDK domain • LinkedIn

• Sristi Rani, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Currently doing internship at STMicroelectronics in PDK domain • LinkedIn

• Barsha Parida, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of Low-power bandgap reference ciecuit in 180nm CMOS Technology. • LinkedIn

• Meerashree Sahoo, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of Low-power bandgap reference in 180nm CMOS Technology. • LinkedIn

• Subhrajita Gantayat, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of Low-power bandgap reference in 180nm CMOS Technology. • LinkedIn

• Sumant Polaki, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of Low-power bandgap reference in 180nm CMOS Technology. • LinkedIn

• Shruti Shubhra, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design • Project: Design and Implementation of Low-power bandgap reference in 180nm CMOS Technology. • LinkedIn

• Divyajit Swain, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Analog and Mixed Signal IC Design domain • LinkedIn

• Puja Kumari, BTech (ECE), Silicon Institute of Technology, Bhabaneswar 2023 Batch • Doing training at Advanced VLSI Lab in Digital Design and Verification • Project: Design and Implementation of Low-power bandgap reference in 180nm CMOS Technology. • LinkedIn

Past Trainees

• Subham Rath, BTech: SIT Bhubaneswar, 2022 Batch, working as a CAD Engineer at Micron Technology • Trained in Analog VLSI Circuit and Layout design. gitHub-page • LinkedIn

• Chandan Singh, BTech: SIT Bhubaneswar, 2022 Batch, working as a IP Verification Engineer at Mentor Graphics • Trained in Digital VLSI Design and Verification • LinkedIn

• Abhinab Das, BTech: SIT Bhubaneswar, 2022 Batch, working aa a RTL Designer at CoreEL Technologies

• Neha Samantaray, BTech: SIT Bhubaneswar, 2022 Batch, working as a Analog Circuit Designer (I/O) at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in Analog Circuit Design, simulation and characterization • LinkedIn

• Satya Ranjan Panda, BTech: SIT Bhubaneswar, 2022 Batch, working as a Yeild Enhancement Engineer at Global Foudries • Trained in Analog Circuit Design, simulation and characterization • LinkedIn

• Soumay Ranjan Khadagray, BTech: SIT Bhubaneswar, 2021 Batch, woking as a PDK Design Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in PDK (DRC/LVS) design domain for leading semiconductor organizations. • LinkedIn

• Pracheeta Mohapatra, BTech: SIT Bhubaneswar, 2021 Batch, woking as a PDK Design Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in Digital VLSI (Pcell/Plib) Design domain for leading semiconductor organizations. • LinkedIn

• Punyadeep Pattnaik, BTech: SIT Bhubaneswar, 2021 Batch, woking as a Design and Verification Engineer at a leading semiconductor organization through [Wipro Technologies](https://www.wipro.com • Trained in Digital VLSI Circuit Design and Verification domain • LinkedIn

• Ajit Kumar Patro, BTech: SIT Bhubaneswar, 2021 Batch, woking as a Standard Cell Library Development Engineer at Intel Corporation • Trained in Analog VLSI Circuit Design, Layout and Verification domain • LinkedIn

• Satabdi Panda, BTech: SIT Bhubaneswar, 2021 Batch, woking as a AMS Layout Engineer at Synopsys Inc. • Trained in Analog VLSI Circuit Design, Layout and Verification and PDK (LVS/PLS) Design domain • LinkedIn

• Vikash Kumar, BTech: SIT Bhubaneswar, 2021 Batch, woking as a PDK (LVS/PLS) Design Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in Analog VLSI Circuit Design, Layout and Verification and PDK (LVS/PLS) Design domain • LinkedIn

• Gautam Kumar, BTech: SIT Bhubaneswar, 2021 Batch, woking as an Application Engineer at Cadence Design System • Trained in Analog VLSI Circuit and Layout Design, and PDK (PEX) Design domain • LinkedIn

• Rajkumar Laldev, BTech: SIT Bhubaneswar, 2021 Batch, woking as a RTL Verification Engineer at CoreEL Technology • Trained in Digital Logic Design using Verilog. • gitHub-page • LinkedIn

• Shubham Kumar, BTech: SIT Bhubaneswar, 2021 Batch, woking as a PDK (Pcell/Plib) Design Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in Digital Logic Design using Verilog and PDK Design domain • LinkedIn

• Chirag Mohanty, BTech: SIT Bhubaneswar, 2021 Batch, woking as a RF Design Engineer at VVDN Technology • Trained in Analog Circuit and Layout Design domain • gitHub-page • LinkedIn

• Smruti Rekha Prusty, BTech: SIT Bhubaneswar, 2021 Batch, woking as a RF Design Engineer at VVDN Technology • Trained in Analog Circuit and Layout Design domain • LinkedIn

• Sachin Modi, BTech: SIT Bhubaneswar, 2021 Batch, woking as a DV Engineer at Marquee Semiconductor • Trained in Digital Logic Design and Verification domain • LinkedIn

• Waqar Ahemad, BTech: SIT Bhubaneswar, 2021 Batch, woking as a DV Engineer at Perfect VIP • Trained in Digital Logic Design and Verification domain • LinkedIn

• Swadesh Kumar Nath, Btech: CET Bhubaneswar, 2021 Batch, • 2021 Batch,* woking as a PDK (LVS/PLS) Design Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in Layout and Verification and PDK (LVS/PLS) Design domain • LinkedIn

• Arpita Padhi, Btech: NIST Berhampur, 2021 Batch, • woking as a Scribe Line Layout Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in analog and standard cell layout design LinkedIn

• Tamanna Samal, Mtech: CET Bhubaneswar, 2021 Batch, • woking as a Scribe Line Layout Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in analog and standard cell layout design LinkedIn

• Rohit Kumar, Btech: SIT Bhubaneswar, 2021 Batch, • Woking as a Scribe Line Layout Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in analog and standard cell layout design LinkedIn

• Nikita Kumari, Btech: Kamla Nehru Institute of Technology, Sultanpur, 2020 Batch, • Woking as a Scribe Line Layout Engineer at a leading semiconductor organization through Sevya Multimedia Pvt. Ltd. • Trained in analog and standard cell layout design LinkedIn

• Aditya Singh, ECE, 2022 • Project: Design & Implementation of Bandgap voltage reference(BGR) in 0.18um CMOS for wide input supply swing

• Ashutosh Jena, ECE, 2020 • Project: Design & Implementation of SRAM controller in 180nm CMOS technology

• Binit Patwari, ECE, 2020 • Project: Evolution of ASIC Design starting from "Verilog to UVM" • Current Company: • Sevya Multinedia Private Limited

• Hritik, ECE, 2020 • Project: Design & Implementation of I2C Protocol in 180nm CMOS Technology

• Manoj Nayak, ECE, 2020 • Project: Design & Implementation of SRAM controller in 180nm CMOS technology

• Smita Panda, ECE, 2020 • Project: Design & Implementation of Bandgap voltage reference(BGR) in 0.18um CMOS for wide input supply swing

• Soumya Prakash Behura, ECE, 2020 • Project: Design & Implementation of I2C Protocol in 180nm CMOS Technology

• Subhra Sutapa Mahapatra, ECE, 2020 • Project: Modelling of Sigma-Delta Analog-to-Digital converters • Current company: • Synopsys

• Swarna Prabha Nanda, ECE, 2022 • Project: Design & Implementation of SRAM controller in 180nm CMOS technology • Current Company: Marquee Semiconductor

• Tapan Karan, ECE, 2022 • Project: Design & Implementation of Bandgap voltage reference(BGR) in 0.18um CMOS for wide input supply swing

• Abhishek Kumar, ECE, 2019 • Project: Design of I2C Slave to interface with serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology • Current Company: • Sevya Multinedia Private Limited

• Anshuman Mishara, ECE, 2019 • Project: Design of I2C Slave to interface with serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology

• Deepika Kumari, ECE, 20219 • Project: Design of Low Power Decoder for SPI/I2C serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology

• Gautam Kumar, ECE, 2019 • Project: Design of SPI Controller for serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology

• Jagyaseni Panda, ECE, 2019 • Project: SRAM Compilation using OpenRAM Compiler • Current Company: • Sevya Multinedia Private Limited

• Manamohan Nath, BTech: SIT Bhubaneswar, 2019 Batch, working as a PDK Development Engineer at ST Microelectronics • Trained in Analog VLSI Circuit and Layout design. • LinkedIn

• Prachi Mrudula, BTech: SIT Bhubaneswar, 2019 Batch, working as a PDK Development Engineer at ST Microelectronics • Trained in Analog VLSI Circuit and Layout design. gitHub-page • LinkedIn

• Pragya Tiwari, ECE, 2019 • Project: Design of sense amplifier for Low Power SPI/I2C serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology •

• Sameer Nameo, ECE, 2019 • Project: Design of SPI Controller for serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology •

• Sneha kumari, BTech: SIT Bhubaneswar, 2019 Batch, working as a Scribe Design Engineer at Micron Technology • Trained in Analog VLSI Circuit and Layout design. • LinkedIn

• Shiva Prasad Das, ECE, 2019 • Project: Design of Low Power SPI/I2C serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology

• Samiksha Agrawal, BTech: SIT Bhubaneswar, 2019 Batch, working as a Scribe Design Engineer at Micron Technology • Trained in Analog VLSI Circuit and Layout design. • LinkedIn

• Suruchi kumari, ECE, 2019 • Project: Design of I2C Slave to interface with serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology

• Unnati kumari Gupta, ECE, 2019 • Project: Design of sense amplifier for Low Power SPI/I2C serial SRAM suited for IOT based embedded system in 0.6um CMOS Technology

• Vishal Sao, BTech: SIT Bhubaneswar, 2019 Batch, working as a PDK Library Development Engineer at ST Microelectronics • Trained in Analog VLSI Circuit and Layout design. gitHub-page • LinkedIn