Publications

Books/Chapters

  • U. Nanda, D. P. Acharya, P.K. Rout, D. Nayak, B. Jena, "Performance-Linked Phased- Locked Loop Architectures: Recent Developments" in Advanced VLSI Design and Testability Issues, (CRC Press), pp. 271-285, 2020

  • D Nayak, D P Achary, P K Rout, U Nanda, "Design and analysis of variability aware FinFET-based SRAM circuit design" in VLSI and Post-CMOS Electronics, Vol. 2: Devices, circuits and interconnects, (IET), Chapter 6, pp.101-122. 2019

  • U. Nanda, D. Nayak, S. K. Pattnaik, S. K. Swain, S. M. Biswal and B. Biswal, "Design and Performance Analysis of Current Starved Voltage Controlled Oscillator" in Microelectronics, Electromagnetics and Telecommunications, (Springer), pp. 235-246. 2019

  • S.S.Rout, D.Tripathy,K.Sethi, "An improved bulk injection cascode mixer for receiver frontend " in National Conference on Device and circuits (IEEE ), pp. 37-41, Feb. 2016, Odisha,India

Journals

  • U. Nanda, D.P. Acharya, D. Nayak, P.K. Rout, "Modelling and Optimization of Phase Locked Loop under Constrained Channel Length and Width of MOSFETs", Silicon (Springer), (Accepted author version posted online: 28 Jan 2021) (SCI Impact Factor 1.499)
  • I. Som, S. Sarangi and T. K. Bhattacharyya, "A 7.1-GHz 0.7-mW Programmable Counter With Fast EOC Generation in 65-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 11, pp. 2397-2401, Nov. 2020, doi: 10.1109/TCSII.2020.2966373.
  • U. Nanda, D.P. Acharya, D. Nayak, "Process Variation Tolerant Wide-band Fast PLL with Reduced Phase Noise using Adaptive Duty Cycle Control Strategy", International Journal of Electronics(Taylor & Francis), (Accepted author version posted online: 07 Jul 2020), (SCI Impact Factor 1.004)
  • D. Nayak, P. K. Rout, S. Sahu, D.P. Acharya, U. Nanda, D. Tripathy, "A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance", Microelectronics Journal (Elsevier), vol. 97, pp. 01-11, Mar 2020. (SCI Impact Factor 1.405)
  • D. Nayak, D.P. Acharya, P. K. Rout, U. Nanda, "A Novel Charge Recycle Read Write Assist Technique for Energy Efficient and Fast 20nm 8T-SRAM Array", Solid-State Electronics (Elsevier), vol. 148, pp. 43-50, Oct 2018. (SCI Impact Factor 1.437)
  • U. Nanda, D.P. Acharya, D. Nayak, P.K. Rout, "High performance PLL for multiband GSM applications", International Journal of Nanoparticles (Inderscience), vol. 10, no. 3, pp. 244-258, Aug 2018, (Scopus, SCImago Journal Rank 0.121)
  • D. Nayak, D.P. Acharya, P.K. Rout, U. Nanda, "A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate", Microelectronics Journal (Elsevier), vol. 73, pp. 43-51, March 2018. (SCI Impact Factor 1.405).
  • D. Nayak, D.P. Acharya, K. Mahapatra, "Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power", Circuit, System and Signal Processing (Springer), vol. 36, Issue 8, pp. 3047-3070, Aug 2017. (SCI Impact Factor 1.681)
  • D. Nayak, D.P. Acharya, K. Mahapatra, "A Read Disturbance Free Differential Read SRAM Cell for Low Power and Reliable Cache in Embedded Processor", AEU - International Journal of Electronics and Communications (Elsevier), vol. 74, pp. 192-197, April 2017. (SCI Impact Factor 2.924).
  • D. Nayak, D.P. Acharya, K. Mahapatra, "An improved energy efficient SRAM cell for access over a wide frequency range", Solid-State Electronics (Elsevier), vol. 126, pp. 14-22, Dec 2016. (SCI Impact Factor 1.437).
  • J Sarangi, Umakanta Nanda, P.K. Rout, "Study of Recent Charge Pump Circuits in Phase Locked Loop", International Journal of Modern Education and Computer Science, vol. 8, pp- 59-65, Aug 2016.
  • P.K.Rout, D.P. Acharya and G. Panda "Fast Physical Design of CMOS ROs for Optimal Performance using Constrained NSGA-II" AEU - International Journal of Electronics and Communications, (Elsevier), vol-69 , pp. 1233–1242, May 2015, (SCI Impact Factor 2.924).
  • P.K.Rout, D.P. Acharya and G. Panda, "Design of Optimal Nano-CMOS Differential VCO for RF Applications" International Journal of Circuits and Architecture Design ( IJCAD) Inderscience, vol. 1, No.3 pp. 242 – 257, April, 2014.
  • P.K.Rout, B.P.Panda, D.P. Acharya and G. Panda, "Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition" International Journal of Signal and Imaging Systems Engineering (IJSISE) (Inderscience) vol. 7 No. 1 Pages:30-37, 2014
  • P.K.Rout, D.P. Acharya and G. Panda "A Multiobjective Optimization Based Fast and Robust Design Methodology for Low Power and Low Phase Noise Current Starved VCO" IEEE Transaction on Semiconductor Manufacturing, vol-27, no-1, pp. 43-50, Feb. 2014. (SCI Impact Factor 1.977)
  • P.K.Rout, D.P. Acharya and G. Panda, "Design of a Novel Current Starved VCO via Constrained Geometric Programming" International Journal of Computer Applications (IJCA), vol-3, pp.37-40, 2011.

Conferences

  • S. Sarangi, I. Som and T. K. Bhattacharyya, "A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning Method," 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022, pp. 44-49
  • S. Sarangi, I Som, and T.K. Bhattacharyya "A Compact and Low-power Transmitter Driver Design for High-Speed SerDes System" International Conference on VLSI Design and Embeded Systems (VLSID-2021), February 20-24, 2021 (virtual event)
  • S. Sarangi, D. Tripathy, S.S. Mahapatra, and S.Rout" A Power and Area Efficient CMOS Bandgap Reference Circuiwith an integrated Voltage Reference Branch", in Proc. of Springer Modelling,Simulation, Intelligent Computing(MoSICom-2020), BITS-Pilani Dubai Campus.
  • D. Nayak, U. Nanda, P. K. Rout, S. M. Biswal, D. Tripathy, S. K. Swain, B. Baral, S. K. Das, "A Novel Driver less SRAM with Indirect Read for Low Energy Consumption and Read Noise Elimination", in Proc. of IEEE International Conference on Devices for Integrated Circuit (DevIC), March. 2019, pp. 314-317 (2019), Kalyani, India
  • D. Tripathy, D. Nayak, S. M. Biswal, S. K. Swain, B. Baral, S. K. Das, "A Low Power LNA using Current Reused Technique for UWB Application", in Proc. of IEEE International Conference on Devices for Integrated Circuit (DevIC), March. 2019, pp. 310-313 (2019), Kalyani, India
  • N. K. Mucheli, U. Nanda, D. Nayak, P. K. Rout, S. K. Swain, S. K. Das, S. M. Biswal, "Smart Power Theft Detection System", in Proc. of IEEE International Conference on Devices for Integrated Circuit (DevIC), March. 2019, pp. 302-305 (2019), Kalyani, India
  • S. M. Biswal, S. K. Swain, B. Baral, D. Nayak, U. Nanda, S. K. Das, D. Tripathy, "Performance Analysis of Staggered Heterojunction based SRG TFET biosensor for health IoT application", in Proc. of IEEE International Conference on Devices for Integrated Circuit (DevIC), March. 2019, pp. 493-496 (2019), Kalyani, India
  • S. K. Swain, S. K. Das, S. M. Biswal, S. Adak, U. Nanda, A. A. Sahoo, D. Nayak, D. Tripathy, "Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET", in Proc. of IEEE International Conference on Devices for Integrated Circuit (DevIC), March. 2019, pp. 510-514 (2019), Kalyani, India
  • S. K. Das, S. K. Swain, S. M. Biswal, D. Nayak, U. Nanda, B. Baral, D. Tripathy, "Effect of High-K Spacer on the Performance of Gate-Stack Uniformly doped DG-MOSFET", in Proc. of IEEE International Conference on Devices for Integrated Circuit (DevIC), March. 2019, pp. 365-369 (2019), Kalyani, India
  • B. Baral, S. M. Biswal, S. K. Swain, D. Nayak, S. K. Das, D. Tripathy, "RF/Analog & Linearity performance analysis of a downscaled JL DG MOSFET on GaAs substrate for Analog/mixed signal SOC applications", in Proc. of IEEE International Conference on Devices for Integrated Circuit (DevIC), March. 2019, pp. 505-509 (2019), Kalyani, India
  • Utpal Das, Shuvabrata Bandopadhaya, Prakash Kumar Rout, "Quality of Service Analysis of Massive MIMO Wireless System with Time Division Duplexing" 2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC), Oct. 2018.
  • D.Tripathy, P.Bhadra, " A High Speed Two Stage Operational Amplifier with High CMRR", in Proc. of IEEE Recent Trends in Electronics,Information and Communication Technology(RTEICT), May-2018, Bangaluru,India
  • S. N. Panda, S. Padhi, V. Phanindra, U. Nanda, S. K. Pattnaik and D. Nayak, "Design and implementation of SRAM macro unit", in Proc. of IEEE International Conference on Trends in Electronics and Informatics (ICEI), May. 2017, pp. 119-123 (2017), Tirunelvely, India
  • S. K. Pattnaik, U. Nanda, D. Nayak, S. R. Mohapatra, A. B. Nayak and A. Mallick, "Design and implementation of different types of full adders in ALU and leakage minimization", in Proc. of IEEE International Conference on Trends in Electronics and Informatics (ICEI), May. 2017, pp. 924-927 (2017), Tirunelvely, India
  • D.Tripathy, T.Manasneha,V.Das, " A single ended TG based 8T SRAM with increased stability and less delay", in Proc. of IEEE Recent Trends in Electronics,Information and Communication Technology(RTEICT), pp.1282-1285, May-2017, Bangaluru , India
  • D. Nayak, D.P. Acharya, K. Mahapatra, "Power efficient design of a novel SRAM cell with higher write ability", in Proc. of IEEE India Conference (INDICON), Dec. 2015, pp. 1-6 (2015), Delhi, India
  • D.Tripathy, S.S.Rout, K.Sethi, "A low power noise cancelling LNA for UWB receiver frontend", in Proc. of IEEE Power,Communication and Information Technolgy Conference(PCITC), pp.442-446, Sept. 2015, Odisha, India
  • D. Nayak, D.P. Acharya, P. K. Rout, K. Mahapatra, "Design of low-leakage and high writable proposed SRAM cell structure", in Proc. of IEEE International conference on Electronics and Communication System (ICECS), Feb. 2014, pp. 1-5, Coimbatore, India
  • P.K.Rout, D.P. Acharya and G. Panda, D. Nayak, "Process Corner Variation Aware Design of Low Power Current Starved VCO" in Proc. of IEEE International conference on Electronics and Communication System (ICECS), Feb. 2014, pp. 1-5, Coimbatore, India
  • P.K.Rout, D.P. Acharya and G. Panda, "Constrained Multi objective Optimization based Design of CMOS Ring Oscillator" International Conference on Computer Communication and Informatics (ICCCI 2014), Sri Shakthi Institute of Engineering and Technology, Coimbatore. pp.1-5, Jan. 2014.
  • P.K. Rout, D. Nayak, D.P. Acharya, "A novel low power 3T inverter", in Proc. of IEEE International conference on Advanced Electronic Systems (ICAES), Sept. 2013, pp. 221-224, Pilani, India
  • P.K.Rout, D.P. Acharya and G. Panda, "Design of Low Power 3.3-4 GHz LC VCO using CMODE " National Conference on Emerging Trends and Applications in Computer Science (NCETACS-2012), St. Anthony's College Shillong, Meghalaya, pp. 717 – 720, March 2013.
  • P.K.Rout, D.P. Acharya and G. Panda, "Design of LC VCO for optimal figure of merit performance using CMODE" International Conference on Recent Advances in Information Technology (RAIT-2012), Dhanbad, India.pp: 761 – 764, March 2012
  • P.K.Rout, D.P. Acharya and G. Panda, "Design of a Low Power Low Phase Noise Current Starved VCO using CMODE" International Conference on Energy, Automation and Signal (ICEAS-2011), SOA University, Bhubaneswar, Dec 2011.
  • P.K.Rout, B.P.Panda, D.P. Acharya and G. Panda, "Analysis and Design of a 1GHz PLL for Fast Phase and Frequency Acquisition" International Conference on Electronic Systems-2011(ICES-2011), NIT, Rourkela. Jan. 2011.
  • P.K.Rout, D.P. Acharya and G. Panda, "Novel PSO based FPGA Placement Techniques" International Conference on Computer and Communication Technology (ICCCT-2010), MNNIT,Allahabad. pp.630-634, Sept. 2010.
  • P.K.Rout, D.P. Acharya and G. Panda, "Digital Circuit Placement in FPGA based on Efficient Particle Swarm Optimization Techniques" International Conference on Industrial and Information Systems-2010(ICIIS-2010), NIT, Surathkal. pp.224 – 227, Jul 2010