Courses and Training

Analog and Mixed-signal VLSI Design, Characterization and Layout (4 January - Present, 2021)

Analog and mixed signal (AMS) VLSI design is one of the rare and highly important domains in VLSI industry. AMS design is comparatively difficult and time consuming because of its design complexity, competitive specifications, technology dependency and full custom design. So the AMS VLSI domain always wants people who have solid understanding on analog devices and circuits, good amount of circuit design knowledge and experienced with circuit characterization and layout design. Due to the above requirement this "Analog and Mixed-signal VLSI" has been started. All the laboratory and projects will be done in commercial EDA tools (Cadence). 0.18um HV SOI process technology is used to design and layout purpose for this course. The first part of the course focused on essential active and passive components important for analog design. In second part it covers simple circuits like current mirrors, single stage amplifiers and differential amplifiers and its design methodology. In third part we are going to cover advanced and complex circuits using the simple circuits. In the final part of this course students will design more application specific systems like BGR, LDO, Oscillator, ADC and DAC. Apart from this circuit design, more focus is giving on circuit characterization and full custom layout design. After completion of this course the participants will able to;

  • understand the biasing of the circuits, small-signal model and large signal behaviors of MOSFETS, frequency response of the circuits
  • design and characterize simple circuits, also able to design layout of different circuits considering layout rules, recommendations and guidelines
  • design current mirrors, error amplifiers, comparators, sample-and-hold circuits etc
  • floor plan, placement and routing of highly complex blocks like, band gap reference (BGR), digital-to-analog converter (DAC), Temperature sensor circuits, Oscillators etc
  • This course was started from 4th January, 2021

Pcell development using SKILL Scripting

Scripting is a necessity for CAD engineers but can also enable circuit designers to do complex activities efficiently. SKILL programming language is based on artificial intelligence language Lisp. SKILL lets designers quickly and easily customizes existing CAD applications and helps them to develop new applications. SKILL scripting language can be used to develop Pcells. A parameterized cell, or PCell, is a programmable cell that lets designers create a customized instance each time they place it. This course was aim to develop Pcells using SKILL scripting in 0.18um CMOS technology. From this training the participants able to;

  • create Pcells using SKILL scripting
  • add labels to pins in a layout
  • generate layout from schematic view from all cells in a library
  • create rectangular and polygon shape with certain Width and Length
  • create CDF information for the Pcell
  • This course was conducted from 12th October to 19th December, 2020

A Long Term Digital VLSI Design Course and Laboratory for Under Graduate Students

From the VLSI industry point of view major part of the VLSI work (more than 80%) is under digital VLSI design. From RTL deign to GDS formation several micro divisions are there to complete the flow. To work in any micro-division a basic understanding of digital VLSI design is very important. This course is specifically designed for UG students to understand, design and characterize combinational and sequential circuits, dynamic logic circuits and different type of memory circuits. Module-1 covers on MOS Structure and MOSFET operations in more details. Module-2 covers the static and dynamic characteristics of an Inverter design, which is most important because the principle uses in the simple inverter can be applicable on any type of circuit. Module-3 covers the design and characterization of both combinational circuits and sequential circuits. Module-4 of this course deals with the dynamic circuits (DOMINO, NORA, ZIPPER, TSPC) design and memory design (SRAM, DRAM). To check theoretical concept of combinational and sequential designs few laboratory experiments also included in this course. The major outcomes of this course are;

  • fully understanding of MOSFET and its operations for digital logic design
  • Fully understanding of static (VTC, Noise Margin) and dynamic characteristics (Delay, power) which will help to design and characterize any type of digital logic
  • Design and timing characterization (setup time, hold time, recover time, removal time) of sequential circuits (Latch, D-FF)
  • Understanding and design of high performance dynamic logic circuits (DOMINO, NORA, ZIPPER, TSPC etc)
  • Understanding and design of static random access memory (SRAM) circuits
  • This course was conducted from 20th July to 15th December, 2020

A Summer Course on Foundation of VLSI for UG, PG and Industry Freshers

The growing VLSI industry always demands people with good fundamentals as well as good engineering knowledge on VLSI domain. For this requirement this summer course "Foundation of VLSI" was started to improve their understanding as well as strengthen their VLSI fundamentals. This course covers from a very starting point of MOSFET operation to the highly complex Static Timing Analysis (STA), Logic Synthesis (LS) and Physical Design (PD). The first part of this course covers intensive discussions on MOSFET operations, combinational circuit designs and sequential logic design and its different timing characteristics. Second part of this course gives a detail view of standard cell library and its importance in digital VLSI design. Additionally basic static timing analysis (STA) is introduced in this part to understand the timing constraints for both combinational and sequential cells in digital VLSI design. The third part of this course deals with the advanced static timing analysis and logic synthesis. The Final part of this course ends with a hands-on session using OpenSTA. The course outcomes are;

  • provides a very strong fundamentals on CMOS technology, MOSFET Operations, combinational and sequential designs
  • provides detail understanding of backend digital design as well as standard cell library and its use
  • provides a detailed knowledge on basic and advanced static timing analysis of digital VLSI design
  • Participants gets a hands-on training facility through OpenSTA to check different timing characteristics of a complex design
  • This course was conducted from 26th February to 7th July, 2020

A summer course on CMOS VLSI Design

This course was designed for UG student with a specific aim to design, simulate, layout and test of a Serial Peripheral Interface (SPI) for a 32-byte Static Random Access Memory (SRAM) using a 0.6um CMOS Technology. This course covers all the theoretical background and the domain knowledge required to complete the project. First part of this course covers a brief of basic circuit and system theory. Second part of this course covers the basic circuit design using the 0.6um CMOS technology. Third part of this course focuses on circuit simulation, layout design and parasitic extraction using Tanner and Mentor graphics. The final part covers the silicon chip testing. The outcomes of this course are;

  • Understanding of SPI and SRAM and its interfacing
  • Design and layout of shift register, SPI controller, 5-bit counter, comparator using commercial EDA tool (Tanner)
  • Design of 5-bit address latch and read-write latch using commercial EDA tool (Tanner)
  • Design of synchronous circuit for signal generation using commercial EDA tool (Tanner)
  • Verification (DRC, LVS) and parasitic extraction (PEX) of SPI using commercial verification tool (Mentor Graphics)
  • understanding the test setup and Silicon testing
  • This course was conducted from 8th June to 28th July, 2019

Analog Integrated Circuits: Analysis, Design and Layout

This course provides a strong analytic foundations in circuits, systems and CMOS design allowing the participants to tackle complex industry challenges in various Deep Sub-micron Technology process. Laboratory exercise and projects are based on industry IP blocks using commercial full-custom EDA tool chain from cadence design systems, providing the participant entire backend experience (design abstraction to chip fabrication). Two commercial sub-micron CMOS semiconductor technologies, 0.18um SOI HV and 0.6um CMOS, are used for the design and layout of the circuit. The theory covered in this course are, Linux and Python basics, circuit and system basics, Integrated circuit devices, CMOS process, basics of analog circuit design, full custom design etc. In laboratory, current mirrors, differential amplifier, source follower and other essential components required for project are designed. Finally, in project a supply and temperature independent low-power and low-noise band gap voltage reference is designed. From this training the participants able to;

  • understand the analog integrated circuit design flow
  • understand and design the basic analog IC components like, current mirrors, single stage amplifiers and differential amplifiers
  • understand the frequency response and feedback analysis
  • design and layout of a standard low-power and low-noise band gap reference (BGR) circuit
  • Fully characterize the BGR circuits (DC analysis, AC analysis, Transient analysis, Stability analysis, Noise analysis etc)
  • This course was conducted from 22nd April to 18th May, 2019

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